During the formation of printed circuit boards (PCBs) or other integrated circuit (IC) packaging processes, the semiconductor devices provided in the printed circuit board can be respectively connected to the outside via a wire-bonding process. In such a process, one or more bonding pads are provided which are in contact with respective parts of the semiconductive device at the outer-most conductive layer thereof. Then, a bonding wire is bonded onto the bond pad so as to allow the semiconductor device to make electric contact with the inner lead of the IC package. Typically, the wire bonding process can be approximately categorized into two main types: the gold wire/gold ball bonding process and the aluminum wire wedge bonding process. The aluminum wire wedge bonding process is widely used in chip-on-board (COB) applications in which the aluminum wire is welded to the bond pad via a combination of ultrasonic vibrations and pressure applied to the wedge. The gold wire/gold ball bonding process is typically accomplished by pressing the wire, which is first formed into a ball, against the bond pad at an elevated temperature. The aluminum wire wedge bonding process is generally less accurate in establishing the bonding position and less uniform in the applied bonding pressure, and, hence, it is more prone to the bond peel-off problem relative to the gold wire/ball bonding process, mainly due to the non-uniformity of mechanical and/or thermal stresses.
The bond peel-off problem occurs when the adhesion force between any adjacent layers in the multi-layer structured semiconductor device is not strong enough to resist the thermal and mechanical stress that may be present during the wire bonding process to bond the bonding wire to the bond pad. This can occur, for example, between the metal bond pad and the underlying polysilicon layer, between a metal layer and a dielectric layer, between a dielectric layer and a polysilicon layer, and between a barrier layer and a dielectric layer, etc.
Bond-pad peeling-off or lift-off, in addition to that discussed above, has been a major unsettling problem besetting the integrated circuit packaging industry involving the wire bonding technology. Many possible solutions have been suggested and implemented, as illustrated in the following prior art references.
U.S. Pat. No. 4,060,828 discloses a semiconductor device having a multi-layer wiring structure with an additional through-hole interconnection formed in the insulating layer beneath the bonding pad of the wiring layer. The purpose of the '828 patent is to provide additional, and protected, electrical contact between the bonding pad and another wiring layer therebelow, such that if the exposed portion of the bonding pad is corroded and thus becoming disconnected, the additional electrical contact formed through the insulation layer can still provide the needed connection. While the '828 patent does not directly address the bond pad peel-off problem, the concept of providing a through-hole interconnection structure in the insulation layer immediately underlying the metal layer as disclosed in the '828 patent has been adopted, though mostly in modified form, by essentially all the prior art processes dealing with solving the problem of bond pad peel-off to provide an anchored structure.
U.S. Pat. No. 4,981,061 discloses a semiconductor device which comprises a first insulating layer formed on the major surface of the semiconductor substrate including an active region. A first contact hole is formed at a position in the first insulating layer corresponding to the active region and a first conductive layer is formed in the first contact hole and a portion of the first insulating layer around the contact hole. Then a second insulating layer is formed on the first conductive layer and the first insulating layer, and a second contact hole is formed at a position in the second insulating layer corresponding to the first conductive layer and located above the first contact hole. Subsequently, a second conductive layer is formed on the second insulating layer and fills the second contact hole. Finally a bonding wire is connected to the second conductive layer in regions located above the first and second contact holes. With the structure disclosed in the '061 patent, the pressure applied to the second insulating layer during wire bonding is supported by columnar portions of the first and second conductive layers filled in the first and second contact holes. Thus, the pressure acting on the second insulating layer is reduced to suppress occurrence of cracks.
U.S. Pat. No. 5,309,205 discloses a bond pad structure which is formed by depositing a barrier layer over an underlying region of a semiconductor device, and then depositing a first conductive layer over the barrier layer. The barrier layer and conductive layer are then patterned and etched to define a conductive region. In the '205 patent, the conductive region is formed in the shape of a grid, and a second conductive layer is deposited over the conductive region and a portion of the exposed underlying region. The second conductive layer makes a good adhesive contact with the underlying region, thus preventing bond pad lift off.
U.S. Pat. No. 5,248,903 discloses a bond pad structure which alleviates bond pad lift problems encountered during wire bonding by providing a composite bond pad, which includes an upper bond pad and a lower bond pad, and an insulating component therebetween. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad. A conductive material is then provided which fills the plurality of openings, and electrically connects the top and bottom bond pads. The at least one opening can be a plurality of conductive vias, a ring-like opening extending around the peripheral region, or one or more elongated slit-like openings.
U.S. Pat. No. 5,309,025 discloses an improved bond pad structure which reduces bond pad lift off problems. The bond pad disclosed in the '025 patent includes a barrier layer, and is formed by first depositing a barrier layer over an underlying region of a semiconductor device, and then depositing a first conductive layer over the barrier layer. The barrier layer and the conductive layer are then patterned and etched to define a conductive region. A plurality of the conductive regions are formed each of which is isolated from the ourside by the formation of an insulative sidewall. A second conductive layer is deposited over the conductive region and a portion of the exposed underlying region. The second conductive layer makes a good adhesive contact with the underlying region, thus preventing bond pad lift off.
U.S. Pat. No. 5,707,894 discloses an improved bonding pad structure and the process for forming the same which reduces the bond pad peeling problem between the bonding pad layer and an underlying layer. The method disclosed in the 894 patent comprises the steps of first forming a plurality of anchor pads on the substrate surface in the bonding pad area. Next, a first insulating layer is formed over the substrate surface and the anchor pads. A plurality of via holes are formed through the first insulating layer which are filled with the same material as a second metal layer, which covers the first insulation layer, so as to form a conductive connection anchor pads and the second metal layer. The via holes have a smaller cross-sectional area than the anchor pads so that the combination of the anchor pads and the second metal form small "hooks" into the first insulating layer that hold the second metal layer (i.e., the bonding pad layer) to the underlying layer.
All of the prior art inventions discussed above failed to notice another important cause for the bond pad peel-off problems. It was observed by the co-inventors of the present invention that, very often, the bond pad peeling problem was found to be caused by cracks formed in or around one or more of the edge portions of the dielectric layer underlying corresponding portions of the metal bonding pad. Once a crack in the edge portion of the dielectric layer is formed due to the thermal and/or mechanical stress during the wire bonding process, it will propagate along the interface between the metal bonding pad and the dielectric layer, and eventually leading to the bond pad to be peeled off from the semiconductor device. Such a bond pad peel-off problem due to crack propagation becomes more profound as the bond pad size becomes smaller.
Furthermore, most of the inventions discussed above involve forming multiple metal-filled holes or vias through the insulation layer underneath the portion of the bond pad where bonding wire is to be attached wherein the heat rise is expected to be high. The multiple metal-filled vias are not interconnected to each other except indirectly at the top through their respective connections to the metal layer. If the multiple metal-filled vias are not laid out properly, or if the wire bonding is not applied on the location as designed, unequal heat transfers from the metal bond pad layer in the different metal-filled vias can cause undesirable thermal stress problems.